Junior at MIT studying Computer Science, building software skills and hands-on projects as I prepare to start my career.
A collection of coursework and personal projects from my time at MIT demonstrating coding, algorithms, and systems work as I gain practical experience.
Building a NASDAQ ITCH 5.0 binary parser and limit order book with price-time priority, replaying full trading sessions with book invariants asserted on every update. Verifying the parser with a GoogleTest suite running under AddressSanitizer in CI, cross-validated against an independently written P
Dec 2025
I created a 4-stage pipelined RISC-V core with two-way set-associative I/D caches, effective hazard management, and branch annulment. It reached a clock speed of 517 ps and processed MNIST inference in 239 microseconds. I also designed an 8-bit SIMD multiply instruction, cutting critical-path delay
Junior at MIT studying Computer Science, building software skills and hands-on projects as I prepare to start my career.
I am Om Patel, a junior studying Computer Science at MIT working toward a Bachelors degree. I have limited professional experience and am preparing to start my career, building technical skills and project work during my studies.
Experience
Software Engineer (Part-Time)
Code Four · Apr 2025 – Present
Software Engineer Intern
Dell Technologies · May 2026 – Aug 2026
Education
Massachusetts Institute of Technology
Bachelor of Science, Computer Science and Engineering, Finance · Class of 2028
Skills
Building a NASDAQ ITCH 5.0 binary parser and limit order book with price-time priority, replaying full trading sessions with book invariants asserted on every update. Verifying the parser with a GoogleTest suite running under AddressSanitizer in CI, cross-validated against an independently written P
Dec 2025
I created a 4-stage pipelined RISC-V core with two-way set-associative I/D caches, effective hazard management, and branch annulment. It reached a clock speed of 517 ps and processed MNIST inference in 239 microseconds. I also designed an 8-bit SIMD multiply instruction, cutting critical-path delay
I created a 4-stage pipelined RISC-V core with two-way set-associative I/D caches, effective hazard management, and branch annulment. It reached a clock speed of 517 ps and processed MNIST inference in 239 microseconds. I also designed an 8-bit SIMD multiply instruction, cutting critical-path delay by 9%, from 645 to 584 ps.
Built a 12–1 cross-sectional momentum strategy on a static S&P 500 universe over Jan 2013 – Jan 2023, rebalanced monthly, measuring 14.8% annualized return, 1.28 Sharpe, and -13.6% maximum drawdown net of 10 bps per-side transaction costs. Stress-tested robustness with 10,000 block-bootstrap Monte C